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| Precision Instrumentation Amplifier AD524 FEATURES Low noise: 0.3 V p-p at 0.1 Hz to 10 Hz Low nonlinearity: 0.003% (G = 1) High CMRR: 120 dB (G = 1000) Low offset voltage: 50 V Low offset voltage drift: 0.5 V/C Gain bandwidth product: 25 MHz Pin programmable gains of 1, 10, 100, 1000 Input protection, power-on/power-off No external components required Internally compensated MIL-STD-883B and chips available 16-lead ceramic DIP and SOIC packages and 20-terminal leadless chip carrier available Available in tape and reel in accordance with EIA-481A standard Standard military drawing also available - INPUT 1 G = 10 13 G = 100 12 G = 1000 11 RG1 16 RG2 3 FUNCTIONAL BLOCK DIAGRAM PROTECTION 4.44k 404 40 Vb 20k 20k OUTPUT 20k 20k 20k 20k SENSE AD524 REFERENCE 00500-001 + INPUT 2 PROTECTION Figure 1. GENERAL DESCRIPTION The AD524 is a precision monolithic instrumentation amplifier designed for data acquisition applications requiring high accuracy under worst-case operating conditions. An outstanding combination of high linearity, high common-mode rejection, low offset voltage drift, and low noise makes the AD524 suitable for use in many data acquisition systems. The AD524 has an output offset voltage drift of less than 25 V/C, input offset voltage drift of less than 0.5 V/C, CMR above 90 dB at unity gain (120 dB at G = 1000), and maximum nonlinearity of 0.003% at G = 1. In addition to the outstanding dc specifications, the AD524 also has a 25 kHz bandwidth (G = 1000). To make it suitable for high speed data acquisition systems, the AD524 has an output slew rate of 5 V/s and settles in 15 s to 0.01% for gains of 1 to 100. As a complete amplifier, the AD524 does not require any external components for fixed gains of 1, 10, 100 and 1000. For other gain settings between 1 and 1000, only a single resistor is required. The AD524 input is fully protected for both power-on and power-off fault conditions. The AD524 IC instrumentation amplifier is available in four different versions of accuracy and operating temperature range. The economical A grade, the low drift B grade, and lower drift, higher linearity C grade are specified from -25C to +85C. The S grade guarantees performance to specification over the extended temperature range -55C to +125C. The AD524 is available in a 16-lead ceramic DIP, 16-lead SBDIP, 16-lead SOIC wide packages, and 20-terminal leadless chip carrier. PRODUCT HIGHLIGHTS 1. The AD524 has guaranteed low offset voltage, offset voltage drift, and low noise for precision high gain applications. The AD524 is functionally complete with pin programmable gains of 1, 10, 100, and 1000, and single resistor programmable for any gain. Input and output offset nulling terminals are provided for very high precision applications and to minimize offset voltage changes in gain ranging applications. The AD524 is input protected for both power-on and power-off fault conditions. The AD524 offers superior dynamic performance with a gain bandwidth product of 25 MHz, full power response of 75 kHz and a settling time of 15 s to 0.01% of a 20 V step (G = 100). 2. 3. 4. 5. Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007 Analog Devices, Inc. All rights reserved. AD524 TABLE OF CONTENTS Features .............................................................................................. 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 8 Connection Diagrams .................................................................. 8 ESD Caution .................................................................................. 8 Typical Performance Characteristics ............................................. 9 Test Circuits ................................................................................. 14 Theory of Operation ...................................................................... 15 Input Protection.......................................................................... 15 Input Offset and Output Offset ................................................ 15 Gain .............................................................................................. 16 Input Bias Currents .................................................................... 17 Common-Mode Rejection ........................................................ 17 Grounding ................................................................................... 18 Sense Terminal............................................................................ 18 Reference Terminal .................................................................... 18 Programmable Gain ................................................................... 20 Autozero Circuits ....................................................................... 20 Error Budget Analysis ................................................................ 21 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 25 REVISION HISTORY 11/07--Rev. E to Rev. F Updated Format .................................................................. Universal Changes to General Description .................................................... 1 Changes to Figure 1 .......................................................................... 1 Changes to Figure 3 and Figure 4 Captions .................................. 8 Changes to Error Budget Analysis Section ................................. 21 Changes to Ordering Guide .......................................................... 25 4/99--Rev. D to Rev. E Rev. F | Page 2 of 28 AD524 SPECIFICATIONS @ VS = 15 V, RL = 2 k and TA = +25C, unless otherwise noted. All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at the final electrical test. Results from those tests are used to calculate outgoing quality levels. Table 1. Parameter GAIN Gain Equation (External Resistor Gain Programming) Min AD524A Typ Max Min AD524B Typ Max Unit 40 ,000 + 1 20% RG 1 to 1000 0.05 0.25 0.5 2.0 0.01 0.01 0.01 5 15 35 100 250 2 5 100 70 85 95 100 50 100 35 100 40 ,000 + 1 20% RG 1 to 1000 0.03 0.15 0.35 1.0 0.005 0.005 0.01 5 10 25 50 100 0.75 3 50 75 95 105 110 25 100 15 100 % % % % % % % ppm/C ppm/C ppm/C ppm/C V V/C mV V dB dB dB dB nA pA/C nA pA/C Gain Range (Pin Programmable) Gain Error 1 G=1 G = 10 G = 100 G = 1000 Nonlinearity G=1 G = 10, G = 100 G = 1000 Gain vs. Temperature G=1 G = 10 G = 100 G = 1000 VOLTAGE OFFSET (May be Nulled) Input Offset Voltage vs. Temperature Output Offset Voltage vs. Temperature Offset Referred to the Input vs. Supply G=1 G = 10 G = 100 G = 1000 INPUT CURRENT Input Bias Current vs. Temperature Input Offset Current vs. Temperature Rev. F | Page 3 of 28 AD524 Parameter INPUT Input Impedance Differential Resistance Differential Capacitance Common-Mode Resistance Common-Mode Capacitance Input Voltage Range Maximum Differential Input Linear (VDL) 2 Maximum Common-Mode Linear (VCM)2 Common-Mode Rejection DC to 60 Hz with 1 k Source Imbalance G=1 G = 10 G = 100 G = 1000 OUTPUT RATING VOUT, RL = 2 k DYNAMIC RESPONSE Small Signal - 3 dB G=1 G = 10 G = 100 G = 1000 Slew Rate Settling Time to 0.01%, 20 V Step G = 1 to 100 G = 1000 NOISE Voltage Noise, 1 kHz RTI RTO RTI, 0.1 Hz to 10 Hz G=1 G = 10 G = 100, 1000 Current Noise 0.1 Hz to 10 Hz SENSE INPUT RIN IIN Voltage Range Gain to Output REFERENCE INPUT RIN IIN Voltage Range Gain to Output Min AD524A Typ Max Min AD524B Typ Max Unit 109 10 109 10 10 10 109 10 109 10 pF pF V V V dB dB dB dB G 12 V - x VD 2 70 90 100 110 10 75 95 105 115 G 12 V - x VD 2 10 V 1 400 150 25 5.0 15 75 1 400 150 25 5.0 15 75 MHz kHz kHz kHz V/s s s 7 90 15 2 0.3 60 20 15 10 1 40 15 10 1 10 10 7 90 15 2 0.3 60 20 15 1 40 15 1 nV/Hz nVHz V p-p V p-p V p-p pA p-p k 20% A V % k 20% A V % Rev. F | Page 4 of 28 AD524 Parameter TEMPERATURE RANGE Specified Performance Storage POWER SUPPLY Power Supply Range Quiescent Current 1 2 Min -25 -65 6 AD524A Typ Max +85 +150 15 3.5 18 5.0 Min -25 -65 6 AD524B Typ Max +85 +150 15 3.5 18 5.0 Unit C C V mA Does not include effects of external resistor, RG. VOL is the maximum differential input voltage at G = 1 for specified nonlinearity. VDL at the maximum = 10 V/G. VD = actual differential input voltage. Example: G = 10, VD = 0.50. VCM = 12 V - (10/2 x 0.50 V) = 9.5 V. @ VS = 15 V, RL = 2 k and TA = +25C, unless otherwise noted. All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at the final electrical test. Results from those tests are used to calculate outgoing quality levels. Table 2. Parameter GAIN Gain Equation (External Resistor Gain Programming) Min AD524C Typ Max Min AD524S Typ Max Unit 40 ,000 + 1 20% RG 1 to 1000 0.02 0.1 0.25 0.5 0.003 0.003 0.01 5 10 25 50 50 0.5 2.0 25 80 100 110 115 40 ,000 + 1 20% RG 1 to 1000 0.05 0.25 0.5 2.0 0.01 0.01 0.01 5 10 25 50 100 2.0 3.0 50 75 95 105 110 % % % % % % % ppm/C ppm/C ppm/C ppm/C V V/C mV V dB dB dB dB Gain Range (Pin Programmable) Gain Error 1 G=1 G = 10 G = 100 G = 1000 Nonlinearity G=1 G = 10, G = 100 G = 1000 Gain vs. Temperature G=1 G = 10 G = 100 G = 1000 VOLTAGE OFFSET (May be Nulled) Input Offset Voltage vs. Temperature Output Offset Voltage vs. Temperature Offset Referred to the Input vs. Supply G=1 G = 10 G = 100 G = 1000 Rev. F | Page 5 of 28 AD524 Parameter INPUT CURRENT Input Bias Current vs. Temperature Input Offset Current vs. Temperature INPUT Input Impedance Differential Resistance Differential Capacitance Common-Mode Resistance Common-Mode Capacitance Input Voltage Range Maximum Differential Input Linear (VDL) 2 Maximum Common-Mode Linear (VCM)2 Common-Mode Rejection DC to 60 Hz with 1 k Source Imbalance G=1 G = 10 G = 100 G = 1000 OUTPUT RATING VOUT, RL = 2 k DYNAMIC RESPONSE Small Signal - 3 dB G=1 G = 10 G = 100 G = 1000 Slew Rate Settling Time to 0.01%, 20 V Step G = 1 to 100 G = 1000 NOISE Voltage Noise, 1 kHz RTI RTO RTI, 0.1 Hz to 10 Hz G=1 G = 10 G = 100, 1000 Current Noise 0.1 Hz to 10 Hz SENSE INPUT RIN IIN Voltage Range Gain to Output Min AD524C Typ Max 15 100 10 100 100 100 35 Min AD524S Typ Max 50 Unit nA pA/C nA pA/C 109 10 109 10 10 10 109 10 109 10 pF pF V V V dB dB dB dB G 12 V - x VD 2 80 100 110 120 10 70 90 100 110 G 12 V - x VD 2 10 V 1 400 150 25 5.0 15 75 1 400 150 25 5.0 15 75 MHz kHz kHz kHz V/s s s 7 90 15 2 0.3 60 20 15 10 1 10 7 90 15 2 0.3 60 20 15 1 nV/Hz nVHz V p-p V p-p V p-p pA p-p k 20% A V % Rev. F | Page 6 of 28 AD524 Parameter REFERENCE INPUT RIN IIN Voltage Range Gain to Output TEMPERATURE RANGE Specified Performance Storage POWER SUPPLY Power Supply Range Quiescent Current 1 2 Min AD524C Typ Max 40 15 Min AD524S Typ Max 40 15 Unit k 20% A V % 10 1 -25 -65 6 15 3.5 +85 +150 18 5.0 10 1 -55 -65 6 15 3.5 +85 +150 18 5.0 C C V mA Does not include effects of external resistor RG. VOL is the maximum differential input voltage at G = 1 for specified nonlinearity. VDL at the maximum = 10 V/G. VD = actual differential input voltage. Example: G = 10, VD = 0.50. VCM = 12 V - (10/2 x 0.50 V) = 9.5 V. Rev. F | Page 7 of 28 AD524 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Supply Voltage Internal Power Dissipation Input Voltage1 (Either Input Simultaneously) |VIN| + |VS| Output Short-Circuit Duration Storage Temperature Range (R) (D, E) Operating Temperature Range AD524A/AD524B/AD524C AD524S Lead Temperature (Soldering, 60 sec) 1 CONNECTION DIAGRAMS Rating 18 V 450 mW <36 V Indefinite -65C to +125C -65C to +150C -25C to +85C -55C to +125C +300C - INPUT 1 + INPUT 2 RG2 3 INPUT NULL 4 16 15 14 RG1 OUTPUT NULL OUTPUT NULL SHORT TO RG2 FOR DESIRED GAIN G = 10 TOP VIEW INPUT NULL 5 (Not to Scale) 12 G = 100 13 AD524 REFERENCE 6 -VS 7 +VS 8 4 +VS INPUT OFFSET NULL 5 14 15 11 10 9 G = 1000 SENSE OUTPUT OUTPUT OFFSET NULL Figure 3. Ceramic (D) and SOIC (RW-16 and D-16) Packages OUTPUT -VS +VS RG1 16 8 +VS 0.103 (2.61) INPUT OFFSET NULL 5 18 OUTPUT OFFSET NULL Figure 4. Leadless Chip Carrier (E) -INPUT 1 +INPUT 2 RG2 3 4 INPUT NULL 5 INPUT NULL 0.170 (4.33) PAD NUMBERS CORRESPOND TO PIN NUMBERS FOR THE D-16 AND RW-16 16-LEAD CERAMIC PACKAGES. 6 REFERENCE 7 -VS ESD CAUTION Figure 2. Metallization Photograph Contact factory for latest dimensions; Dimensions shown in inches and (mm) Rev. F | Page 8 of 28 00500-002 00500-004 OUTPUT NULL 14 OUTPUT NULL 15 G = 10 G = 100 13 12 G = 1000 11 SENSE 10 9 OUTPUT 7 +VS 19 -VS SENSE NC Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3 2 1 RG1 OUTPUT NULL +INPUT -INPUT NC Maximum input voltage specification refers to maximum voltage to which either input terminal may be raised with or without device power applied. For example, with 18 volt supplies maximum, VIN is 18 V; with zero supply voltage maximum, VIN is 36 V. 20 19 18 RG2 4 INPUT NULL 5 NC 6 INPUT NULL 7 REFERENCE 8 9 10 11 12 13 OUTPUT NULL G = 10 NC G = 100 G = 1000 SHORT TO RG2 FOR DESIRED GAIN AD524 TOP VIEW (Not to Scale) 17 16 15 14 NC = NO CONNECT 00500-003 -VS AD524 TYPICAL PERFORMANCE CHARACTERISTICS 20 8 15 INPUT VOLTAGE (V) QUIESCENT CURRENT (mA) 00500-005 6 10 +25C 4 5 2 00500-008 0 0 5 10 SUPPLY VOLTAGE (V) 15 20 0 0 5 10 SUPPLY VOLTAGE (V) 15 20 Figure 5. Input Voltage Range vs. Supply Voltage, G = 1 Figure 8. Quiescent Current vs. Supply Voltage 20 16 14 OUTPUT VOLTAGE SWING (V) 15 INPUT BIAS CURRENT (nA) 00500-006 12 10 8 6 4 00500-009 10 5 2 0 0 0 5 10 SUPPLY VOLTAGE (V) 15 20 0 5 10 SUPPLY VOLTAGE (V) 15 20 Figure 6. Output Voltage Swing vs. Supply Voltage Figure 9. Input Bias Current vs. Supply Voltage 30 40 30 INPUT BIAS CURRENT (nA) 00500-007 OUTPUT VOLTAGE SWING (V p-p) 20 10 0 -10 -20 00500-010 20 10 -30 -40 0 10 100 1k LOAD RESISTANCE () 10k -75 -25 25 TEMPERATURE (C) 75 125 Figure 7. Output Voltage Swing vs. Load Resistance Figure 10. Input Bias Current vs. Temperature Rev. F | Page 9 of 28 AD524 16 14 INPUT BIAS CURRENT (nA) -140 -120 -100 G = 1000 G = 100 G = 10 G=1 12 10 8 6 4 00500-011 CMRR (dB) -80 -60 -40 -20 0 0 0 5 10 INPUT VOLTAGE (V) 15 20 0 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 11. Input Bias Current vs. Input Voltage Figure 14. CMRR vs. Frequency, RTI, Zero to 1000 Source Imbalance 30 0 FULL POWER RESPONSE (V p-p) VOS FROM FINAL VALUE (V) G = 1, 10, 100 20 1 2 3 4 5 00500-012 10 0 1 2 3 4 5 6 WARM-UP TIME (Minutes) 7 8 0 1k G = 1000 G = 100 G = 10 10k 100k FREQUENCY (Hz) 1M Figure 12. Offset Voltage, RTI, Turn-On Drift Figure 15. Large Signal Frequency Response 10 8 SLEW RATE (V/s) 1000 GAIN (V/V) 100 10 1 6 4 G = 1000 2 00500-013 0 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 0 1 10 GAIN (V/V) 100 1000 Figure 13. Gain vs. Frequency Figure 16. Slew Rate vs. Gain Rev. F | Page 10 of 28 00500-016 00500-015 6 BANDWIDTH LIMITED 00500-014 2 AD524 160 100k POWER SUPPLY REJECTION RATIO (dB) 140 120 100 80 60 40 +VS = 15V DC + 1V p-p SINEWAVE CURRENT NOISE SPECTRAL DENSITY (fA/ Hz) 10k G= 1000 G= 100 G= 10 1k G= 1 100 00500-020 0 10 00500-017 20 100 1k FREQUENCY (Hz) 10k 100k 0 1 10 100 1k 10k FREQUENCY (Hz) Figure 17. Positive PSRR vs. Frequency Figure 20. Input Current Noise vs. Frequency 160 POWER SUPPLY REJECTION RATIO (dB) 140 120 100 80 G= G= -VS = -15V DC + 1V p-p SINEWAVE 5mV 0.1Hz TO 10Hz 1s 1000 G= 100 10 1 60 G= 40 20 0 10 00500-018 100 1k FREQUENCY (Hz) 10k 100k VERTICAL SCALE; 1 DIVISION = 5V Figure 18. Negative PSRR vs. Frequency Figure 21. Low Frequency Noise, G = 1 (System Gain = 1000) 1000 0.1Hz TO 10Hz 10mV 1s 100 G=1 VOLT NSD (nV/ Hz) G = 10 10 G = 100, 1000 G = 1000 1 00500-019 1 10 100 1k 10k 100k FREQUENCY (Hz) VERTICAL SCALE; 1 DIVISION = 0.1V Figure 19. RTI Noise Spectral Density vs. Gain Figure 22. Low Frequency Noise, G = 1000 (System Gain = 100,000) Rev. F | Page 11 of 28 00500-022 0.1 00500-021 AD524 -12 TO +12 1% -8 TO +8 -4 TO +4 OUTPUT STEP (V) +4 TO -4 +8 TO -8 1% +12 TO -12 0.1% 0.01% 00500-023 0.1% 0.01% 1mV 10V 10s SETTLING TIME (s) Figure 23. Settling Time, Gain = 1 Figure 26. Large Signal Pulse Response and Settling Time, Gain = 10 -12 TO +12 1% 1mV 10V 10s 0.1% 0.01% -8 TO +8 -4 TO +4 OUTPUT STEP (V) +4 TO -4 +8 TO -8 1% +12 TO -12 0.1% 0.01% 00500-027 00500-024 0 5 10 SETTLING TIME (s) 15 00500-026 0 5 10 15 20 20 Figure 24. Large Signal Pulse Response and Settling Time, Gain =1 Figure 27. Settling Time, Gain = 100 -12 TO +12 1% -8 TO +8 -4 TO +4 OUTPUT STEP (V) +4 TO -4 +8 TO -8 1% +12 TO -12 0.1% 0.01% 00500-025 0.1% 0.01% 1mV 10V 10s 0 5 10 SETTLING TIME (s) 15 20 Figure 25. Settling Time, Gain = 10 Figure 28. Large Signal Pulse Response and Settling Time, Gain = 100 Rev. F | Page 12 of 28 00500-028 AD524 -12 TO +12 1% -8 TO +8 -4 TO +4 OUTPUT STEP (V) +4 TO -4 +8 TO -8 1% +12 TO -12 0.1% 0.01% 00500-029 0.1% 0.01% 5mV 10V 20s 0 10 20 30 40 50 60 70 80 SETTLING TIME (s) Figure 29. Settling Time, Gain = 1000 Figure 30. Large Signal Pulse Response and Settling Time, Gain = 1000 Rev. F | Page 13 of 28 00500-030 AD524 TEST CIRCUITS 10k 0.01% INPUT 20V p-p 100k 0.1% RG1 G = 10 G = 100 11k 0.1% 1k 0.1% 100 0.1% G = 1000 RG2 1 16 13 12 11 3 2 1k 10T 10k 0.1% VOUT +VS - 8 10 AD524 6 7 9 -VS Figure 31. Settling Time Test Circuit +VS I1 50A VB I2 50A R52 20k + R53 20k A3 A1 + C3 A2 C4 SENSE VO -IN CH2, CH3, CH4 CH1 I3 50A R57 20k Q1, Q3 RG1 R56 20k 4.44k 404 40 Q2, Q4 RG2 R54 20k R55 20k REFERENCE +IN G = 100 G = 1000 CH2, CH3, CH4 I4 50A CH1 -VS Figure 32. Simplified Circuit of Amplifier; Gain Is Defined as ((R56 + R57)/(RG)) +1; For a Gain of 1, RG Is an Open Circuit Rev. F | Page 14 of 28 00500-032 00500-031 + AD524 THEORY OF OPERATION The AD524 is a monolithic instrumentation amplifier based on the classic 3-op amp circuit. The advantage of monolithic construction is the closely matched components that enhance the performance of the input preamplifier. The preamplifier section develops the programmed gain by the use of feedback concepts. The programmed gain is developed by varying the value of RG (smaller values increase the gain) while the feedback forces the collector currents (Q1, Q2, Q3, and Q4) to be constant, which impresses the input voltage across RG. As RG is reduced to increase the programmed gain, the transconductance of the input preamplifier increases to the transconductance of the input transistors. This has three important advantages. First, this approach allows the circuit to achieve a very high open-loop gain of 3 x 108 at a programmed gain of 1000, thus reducing gain-related errors to a negligible 30 ppm. Second, the gain bandwidth product, which is determined by C3 or C4 and the input transconductance, reaches 25 MHz. Third, the input voltage noise reduces to a value determined by the collector current of the input transistors for an RTI noise of 7 nV/Hz at G = 1000. from excessive currents. Standard practice is to place series limiting resistors in each input, but to limit input current to below 5 mA with a full differential overload (36 V) requires over 7k of resistance, which adds 10 nVHz of noise. To provide both input protection and low noise, a special series protection FET is used. A unique FET design was used to provide a bidirectional current limit, thereby protecting against both positive and negative overloads. Under nonoverload conditions, three channels (CH2, CH3, CH4) act as a resistance (1 k) in series with the input as before. During an overload in the positive direction, a fourth channel, CH1, acts as a small resistance (3 k) in series with the gate, which draws only the leakage current, and the FET limits IDSS. When the FET enhances under a negative overload, the gate current must go through the small FET formed by CH1 and when this FET goes into saturation, the gate current is limited and the main FET goes into controlled enhancement. The bidirectional limiting holds the maximum input current to 3 mA over the 36 V range. INPUT OFFSET AND OUTPUT OFFSET Voltage offset specifications are often considered a figure of merit for instrumentation amplifiers. While initial offset may be adjusted to zero, shifts in offset voltage due to temperature variations causes errors. Intelligent systems can often correct this factor with an autozero cycle, but there are many smallsignal high-gain applications that do not have this capability. INPUT PROTECTION As interface amplifiers for data acquisition systems, instrumentation amplifiers are often subjected to input overloads, that is, voltage levels in excess of the full scale for the selected gain range. At low gains (10 or less), the gain resistor acts as a current limiting element in series with the inputs. At high gains, the lower value of RG does not adequately protect the inputs +VS 1 - 10 100 16 13 12 8 10 +Vs 16.2k 9 3+ 8 1 AD712 1F 5+ 1000 11 RG2 3 2 AD524 6 7 1F 1/2 2- 9.09k + 6- 1/2 4 7 G = 1, 10, 100 -VS G = 1000 100 1k 1.62M 1F -VS 16.2k 1.82k 00500-033 Figure 33. Noise Test Circuit Rev. F | Page 15 of 28 AD524 Voltage offset and drift comprise two components each; input and output offset and offset drift. Input offset is the component of offset that is directly proportional to gain, that is, input offset as measured at the output at G = 100 is 100 times greater than at G = 1. Output offset is independent of gain. At low gains, output offset drift is dominant, at high gains, input offset drift dominates. Therefore, the output offset voltage drift is normally specified as drift at G = 1 (where input effects are insignificant), whereas input offset voltage drift is given by drift specification at a high gain (where output offset effects are negligible). All input related numbers are referred to the input (RTI) that is the effect on the output is G times larger. Voltage offset vs. power supply is also specified at one or more gain settings and is also RTI. By separating these errors, one can evaluate the total error independent of the gain setting used. In a given gain configuration, both errors can be combined to give a total error referred to the input (RTI) or output (RTO) by the following formulas: Total error RTI = input error + (output error/gain) Total error RTO = (gain x input error) + output error As an illustration, a typical AD524 might have a +250 V output offset and a -50 V input offset. In a unity gain configuration, the total output offset would be 200 V or the sum of the two. At a gain of 100, the output offset would be -4.75 mV or: +250 V + 100(-50 V) = -4.75 mV. The AD524 provides for both input and output offset adjustment. This simplifies very high precision applications and minimizes offset voltage changes in switched gain applications. In such applications, the input offset is adjusted first at the highest programmed gain, then the output offset is adjusted at G = 1. 1.5k 1k RG2 +INPUT The AD524 can be configured for gains other than those that are internally preset; there are two methods to do this. The first method uses just an external resistor connected between Pin 3 and Pin 16 (see Figure 35), which programs the gain according to the following formula: RG = 40 k G = -1 For best results, RG should be a precision resistor with a low temperature coefficient. An external RG affects both gain accuracy and gain drift due to the mismatch between it and the internal thin-film resistors. Gain accuracy is determined by the tolerance of the external RG and the absolute accuracy of the internal resistors (20%). Gain drift is determined by the mismatch of the temperature coefficient of RG and the temperature coefficient of the internal resistors (-50 ppm/C typical). +VS -INPUT RG1 2.105k 1 16 13 12 11 3 2 7 8 10 6 9 AD524 VOUT REFERENCE -VS 40,000 G= + 1 = 20 20% 2.105 Figure 35. Operating Connections for G = 20 The second method uses the internal resistors in parallel with an external resistor (see Figure 36). This technique minimizes the gain adjustment range and reduces the effects of temperature coefficient sensitivity. +VS -INPUT 1 8 GAIN The AD524 has internal high accuracy pretrimmed resistors for pin programmable gains of 1, 10, 100, and 1000. One of the preset gains can be selected by pin strapping the appropriate gain terminal and RG2 together (for G = 1, RG2 is not connected). +VS 8 4 RG1 G = 10 4k RG2 +INPUT *R| G = 10 = 4444.44 *R|G = 100 = 404.04 *R|G = 1000 = 40.04 *NOMINAL (20%) 16 13 12 11 3 2 AD524 7 10 6 9 VOUT REFERENCE -INPUT RG1 G = 10 G = 100 G = 1000 RG2 +INPUT 1 16 13 12 11 3 2 10k 5 Figure 36. Operating Connections for G = 20, Low Gain Temperature Coefficient Technique 10 6 9 AD524 7 VOUT OUTPUT SIGNAL COMMON -VS Figure 34. Operating Connections for G = 100 00500-034 Rev. F | Page 16 of 28 00500-036 INPUT OFFSET NULL -VS G= 40,000 + 1 = 20 17% 4000||4444.44 00500-035 AD524 The AD524 can also be configured to provide gain in the output stage. Figure 37 shows an H pad attenuator connected to the reference and sense lines of the AD524. R1, R2, and R3 should be made as low as possible to minimize the gain variation and reduction of CMRR. Varying R2 precisely sets the gain without affecting CMRR. CMRR is determined by the match of R1 and R3. +VS -INPUT RG1 G = 10 G = 100 G = 1000 RG2 +INPUT G= (R2||40k) + R1 + R3 (R2||40k) 1 16 13 12 11 3 2 7 8 +VS 2 3 11 12 13 16 1 + 8 10 AD524 - 7 9 6 LOAD TO POWER SUPPLY GROUND R1 2.26k R2 5k RL R3 2.26k (R1 + R2 + R3)||RL 2k 00500-037 Figure 40. Indirect Ground Returns for Bias Currents-AC-Coupled VOUT AD524 10 6 9 -VS Figure 37. Gain of 2000 Although instrumentation amplifiers have differential inputs, there must be a return path for the bias currents. If this is not provided, those currents charge stray capacitances, causing the output to drift uncontrollably or to saturate. Therefore, when amplifying floating input sources such as transformers and thermocouples, as well as ac-coupled sources, there must still be a dc path from each input to ground. Table 4. Output Gain Resistor Values Output Gain 2 5 10 R2 5 k 1.05 k 1 k R1, R3 2.26 k 2.05 k 4.42 k Nominal Gain 2.02 5.01 10.1 COMMON-MODE REJECTION Common-mode rejection is a measure of the change in output voltage when both inputs are changed equal amounts. These specifications are usually given for a full-range input voltage change and a specified source imbalance. Common-mode rejection ratio (CMRR) is a ratio expression whereas commonmode rejection (CMR) is the logarithm of that ratio. For example, a CMRR of 10,000 corresponds to a CMR of 80 dB. In an instrumentation amplifier, ac common-mode rejection is only as good as the differential phase shift. Degradation of ac common-mode rejection is caused by unequal drops across differing track resistances and a differential phase shift due to varied stray capacitances or cable capacitances. In many applications, shielded cables are used to minimize noise. This technique can create common-mode rejection errors unless the shield is properly driven. Figure 41 and Figure 42 show active data guards that are configured to improve ac common-mode rejection by bootstrapping the capacitances of the input cabling, thus minimizing differential phase shift. -INPUT 9 INPUT BIAS CURRENTS Input bias currents are those currents necessary to bias the input transistors of a dc amplifier. Bias currents are an additional source of input error and must be considered in a total error budget. The bias currents, when multiplied by the source resistance, appear as an offset voltage. What is of concern in calculating bias current errors is the change in bias current with respect to signal voltage and temperature. Input offset current is the difference between the two input bias currents. The effect of offset current is an input offset voltage whose magnitude is the offset current times the source impedance imbalance. +VS 2 3 11 12 13 16 1 + 8 10 +VS 1 12 AD524 6 - 8 10 G = 100 100 - 7 LOAD RG2 AD524 3 2 9 6 VOUT REFERENCE 00500-041 00500-038 -VS AD711 TO POWER SUPPLY GROUND +INPUT + 7 -VS Figure 38. Indirect Ground Returns for Bias Currents--Transformer Coupled +VS 2 3 11 12 13 16 1 Figure 41. Shield Driver, G 100 -INPUT 100 +VS 1 16 + 8 10 9 6 AD712 RG1 - 8 10 AD524 - 7 12 AD524 6 7 9 VOUT REFERENCE 00500-042 LOAD 100 00500-039 -VS RG2 +INPUT 3 2 -VS + TO POWER SUPPLY GROUND -VS Figure 42. Differential Shield Driver Rev. F | Page 17 of 28 Figure 39. Indirect Ground Returns for Bias Currents--Thermocouple 00500-040 -VS AD524 GROUNDING Many data acquisition components have two or more ground pins that are not connected together within the device. These grounds must be tied together at one point, usually at the system power-supply ground. Ideally, a single solid ground would be desirable. However, because current flows through the ground wires and etch stripes of the circuit cards, and because these paths have resistance and inductance, hundreds of millivolts can be generated between the system ground point and the data acquisition components. Separate ground returns should be provided to minimize the current flow in the path from the sensitive points to the system ground point. In this way, supply currents and logic-gate return currents are not summed into the same return path as analog signals where they would cause measurement errors. Because the output voltage is developed with respect to the potential on the reference terminal, an instrumentation amplifier can solve many grounding problems. ANALOG P.S. +15V C -15V DIGITAL P.S. +5V C SENSE TERMINAL The sense terminal is the feedback point for the instrument amplifier's output amplifier. Normally, it is connected to the instrument amplifier output. If heavy load currents are to be drawn through long leads, voltage drops due to current flowing through lead resistance can cause errors. The sense terminal can be wired to the instrument amplifier at the load, thus putting the IxR drops inside the loop and virtually eliminating this error source. V+ VIN+ 2 3 12 8 10 (SENSE) OUTPUT CURRENT BOOSTER 9 6 AD524 7 X1 RL 00500-044 VIN- 1 (REF) V- Figure 44. AD524 Instrumentation Amplifier with Output Current Booster 0.1 0.1 F F 8 2 7 0.1 0.1 F F DIG COM 1F 1F 1F AD524 1 6 10 9 7 9 11 15 1 AD583 SAMPLE AND HOLD AD574A DIGITAL DATA OUTPUT Typically, IC instrumentation amplifiers are rated for a full 10 volt output swing into 2 k. In some applications, however, the need exists to drive more current into heavier loads. Figure 44 shows how a high current booster may be connected inside the loop of an instrumentation amplifier to provide the required current boost without significantly degrading overall performance. Nonlinearities and offset and gain inaccuracies of the buffer are minimized by the loop gain of the AD524 output amplifier. Offset drift of the buffer is similarly reduced. REFERENCE TERMINAL The reference terminal can be used to offset the output by up to 10 V. This is useful when the load is floating or does not share a ground with the rest of the system. It also provides a direct means of injecting a precise offset. It must be remembered that the total output swing is 10 V to be shared between signal and reference offset. When the AD524 is of the 3-amplifier configuration it is necessary that nearly zero impedance be presented to the reference terminal. Any significant resistance from the reference terminal to ground increases the gain of the noninverting signal path, thereby upsetting the common-mode rejection of the AD524. In the AD524, a reference source resistance unbalances the CMR trim by the ratio of 20 k/RREF. For example, if the reference source impedance is 1 , CMR is reduced to 86 dB (20 k/1 = 86 dB). An operational amplifier can be used to provide that low impedance reference point, as shown in Figure 45. The input offset voltage characteristics of that amplifier adds directly to the output offset voltage performance of the instrumentation amplifier. *IF INDEPENDENT; OTHERWISE, RETURN AMPLIFIER REFERENCE TO MECCA AT ANALOG P.S. COMMON. Figure 43. Basic Grounding Practice Rev. F | Page 18 of 28 00500-043 OUTPUT REFERENCE ANALOG GROUND* SIGNAL GROUND AD524 +VS VIN+ 2 3 12 SENSE 8 10 +INPUT 2 3 + SENSE 10 AD524 6 7 AD524 9 R1 9 13 VX IL VIN- 1 REF LOAD -INPUT 1 - 6 REF A2 00500-045 -VS AD711 IL = R1 = R1 = AD711 VOFFSET Figure 45. Use of Reference Terminal to Provide Output Offset (1 + 40,000 ) RG Figure 46. Voltage-to-Current Converter An instrumentation amplifier can be turned into a voltageto-current converter by taking advantage of the sense and reference terminals, as shown in Figure 46. By establishing a reference at the low side of a current setting resistor, an output current may be defined as a function of input voltage, gain, and the value of that resistor. Because only a small current is demanded at the input of the buffer amplifier (A2) the forced current, IL, largely flows through the load. Offset and drift specifications of A2 must be added to the output offset and drift specifications of the AD524. -IN +IN 1 2 3 PROTECTION PROTECTION +VS 4.44k 16 15 14 13 12 11 R2 10k OUTPUT OFFSET TRIM NC G = 10 K1 G = 100 K2 G = 1000 K3 INPUT OFFSET TRIM R1 10k 4 20k 5 6 20k 20k 20k 404 40 RELAY SHIELDS 20k -VS +VS 1F 35V ANALOG COMMON C1 C2 7 8 20k +5V 10 9 A1 AD524 OUT K1 D1 K2 D2 K3 D3 K1 - K3 = THERMOSEN DM2C 4.5V COIL D1 - D3 = IN4148 GAIN TABLE A B GAIN 0 0 10 0 1 1000 1 0 100 111 INPUTS A GAIN RANGE B 1 2 16 15 Y0 1 2 3 4 5 6 7 16 Y1 74LS138 14 Y2 DECODER 13 4 3 7407N BUFFER DRIVER 5 10F +5V 6 7 00500-046 VX VIN LOAD NC = NO CONNECT LOGIC COMMON Figure 47. Three-Decade Gain Programmable Amplifier Rev. F | Page 19 of 28 00500-047 AD524 PROGRAMMABLE GAIN Figure 47 shows the AD524 being used as a software programmable gain amplifier. Gain switching can be accomplished with mechanical switches such as DIP switches or reed relays. It should be noted that the on resistance of the switch in series with the internal gain resistor becomes part of the gain equation and has an effect on gain accuracy. The AD524 can also be connected for gain in the output stage. Figure 48 shows an AD711 used as an active attenuator in the output amplifier's feedback loop. The active attenuation presents very low impedance to the feedback resistors, therefore minimizing the common-mode rejection ratio degradation. -IN +IN (+INPUT) (-INPUT) 1 2 3 +INPUT (-INPUT) 1 G = 10 13 G = 100 12 G = 1000 11 RG1 16 RG2 3 PROTECTION 4.44k 404 40 Vb 20k 20k 20k 9 AD524 20k 10 VOUT 20k 20k 6 -INPUT 2 (+INPUT) PROTECTION +VS 17 4 3 2 AD712 1/2 DAC A DB0 DB7 DATA INPUTS PROTECTION PROTECTION +VS 4.44k 16 15 14 13 12 14 7 15 16 6 18 256:1 CS OUTPUT OFFSET NULL TO -V R2 10k WR DAC A /DAC B AD7528 DAC B 5 1 19 20 4 10k 5 20k 20k 20k + - 20k 20k 404 40 Figure 49. Programmable Output Gain Using a DAC 11 10 9 6 -VS +VS 1F 35V 7 8 20k AD524 VOUT 20k 10pF +VS - 15 13 11 9 VSS VDD 1 8 GND 16 2 14 12 10 39.2k 28.7k 316k 1k 1k 1k AD711 -VS + Another method for developing the switching scheme is to use a DAC. The AD7528 dual DAC, which acts essentially as a pair of switched resistive attenuators having high analog linearity and symmetrical bipolar transmission, is ideal in this application. The multiplying DAC's advantage is that it can handle inputs of either polarity or zero without affecting the programmed gain. The circuit shown uses an AD7528 to set the gain (DAC A) and to perform a fine adjustment (DAC B). AUTOZERO CIRCUITS In many applications, it is necessary to provide very accurate data in high gain configurations. At room temperature, the offset effects can be nulled by the use of offset trim potentiometers. Over the operating temperature range, however, offset nulling becomes a problem. The circuit of Figure 50 shows a CMOS DAC operating in bipolar mode and connected to the reference terminal to provide software controllable offset adjustments. 00500-048 AD7590 3 4 5 6 7 VDD A2 A3 A4 WR Figure 48. Programmable Output Gain Rev. F | Page 20 of 28 00500-049 INPUT OFFSET NULL AD712 1/2 AD524 +VS +INPUT RG1 G = 10 G = 100 G = 1000 RG2 -INPUT -VS 39k VREF +VS 15 4 11 12 13 3 14 16 2 16 13 12 11 3 1 +VS +10V 8 + 8 10 350 9 350 2 + 10k 4 5 10 AD524 - 7 RG1 G = 100 16 13 12 11 6 350 350 RG2 AD524C 6 9 14-BIT ADC 0V TO 2V F.S. 3 1 -VS R3 20k C1 1 2 - 7 R5 20k 1/2 MSB DATA INPUTS LSB CS WR +VS 2- 3+ 8 1 Figure 52. Typical Bridge Application OUT1 OUT2 AD7524 R4 10k AD712 6- 7 5+ 4 ERROR BUDGET ANALYSIS To illustrate how instrumentation amplifier specifications are applied, review a typical case where an AD524 is required to amplify the output of an unbalanced transducer. Figure 52 shows a differential transducer, unbalanced by 100 , supplying a 0 mV to 20 mV signal to an AD524C. The output of the IA feeds a 14-bit ADC with a 0 V to 2 V input voltage range. The operating temperature range is -25C to +85C. Therefore, the largest change in temperature, T, within the operating range is from ambient to +85C (85C - 25C = 60C). In many applications, differential linearity and resolution are of prime importance in cases where the absolute value of a variable is less important than changes in value. In these applications, only the irreducible errors (45 ppm = 0.004%) are significant. Furthermore, if a system has an intelligent processor monitoring the analog-to-digital output, the addition of an autogain/autozero cycle removes all reducible errors and may eliminate the requirement for initial calibration. This also reduces errors to 0.004%. AD712 GND 1/2 R6 5k Figure 50. Software Controllable Offset In many applications, complex software algorithms for autozero applications are not available. For those applications, Figure 51 provides a hardware solution. +VS 2 15 16 14 13 RG1 16 13 12 8 10 AD524 6 7 VOUT 9 RG2 11 3 1 0.1F LOW LEAKAGE - 1k 12 11 9 10 CH -VS AD711 + VDD VSS GND 8 1 2 AD7510KD A1 A2 A3 A4 00500-051 200s ZERO PULSE Figure 51. Autozero Circuit Rev. F | Page 21 of 28 00500-050 -VS 00500-052 AD589 -VS + - AD524 Table 5. Error Budget Analysis Effect on Absolute Accuracy at TA = 25C 2500 ppm - - 2500 ppm - 1000 ppm - 75 ppm - 50 ppm - 87.5 ppm - 444 ppm - 6656.5 ppm Effect on Absolute Accuracy at TA = 85C 2500 ppm 1500 ppm - 2500 ppm 1500 ppm 1000 ppm 750 ppm 75 ppm 30 ppm 50 ppm 30 ppm 87.5 ppm 50 ppm 444 ppm - 10516.5 ppm Effect on Resolution - - 30 ppm - - - - - - - - - - - 15 ppm 45 ppm Error Source Gain Error Gain Instability Gain Nonlinearity Input Offset Voltage Input Offset Voltage Drift Output Offset Voltage 1 Output Offset Voltage Drift1 Bias Current-Source Imbalance Error Bias Current-Source Imbalance Drift Offset Current-Source Imbalance Error Offset Current-Source Imbalance Drift Offset Current-Source Resistance-Error Offset Current-Source Resistance-Drift Common Mode Rejection 5 V DC Noise, RTI (0.1 Hz to 10 Hz) AD524C Specifications 0.25% 25 ppm 0.003% 50 V, RTI 0.5 V/C - 2.0 mV 25 V/C 15 nA 100 pA/C 10 nA 100 pA/C 10 nA 100 pA/C 115 dB 0.3 V p-p Calculation 0.25% = 2500 ppm (25 ppm/C)(60C) = 1500 ppm 0.003% = 30 ppm 50 V/20 mV = 2500 ppm (0.5 V/C)(60C) = 30 V 30 V/20 mV = 1500 ppm 2.0 mV/20 mV = 1000 ppm (25 V/C)(60C)= 1500 V 1500 V/20 mV = 750 ppm (15 nA)(100 ) = 1.5 V 1.5 V/20 mV = 75 ppm (100 pA/C)(100 )(60C) = 0.6 V 0.6 V/20 mV = 30 ppm (10 nA)(100 ) = 1 V 1 V/20 mV = 50 ppm (100 pA/C)(100 )(60C) = 0.6 V 0.6 V/20 mV = 30 ppm (10 nA)(175 ) = 3.5 V 3.5 V/20 mV = 87.5 ppm (100 pA/C)(175 )(60C) = 1 V 1 V/20 mV = 50 ppm 115 dB = 1.8 ppm x 5 V = 8.8 V 8.8 V/20 mV = 444 ppm 0.3 V p-p/20 mV = 15 ppm Total Error 1 Output offset voltage and output offset voltage drift are given as RTI figures. Rev. F | Page 22 of 28 AD524 Figure 53 shows a simple application in which the variation of the cold-junction voltage of a Type J thermocouple-iron constantan is compensated for by a voltage developed in series by the temperature-sensitive output current of an AD590 semiconductor temperature sensor. RA NOMINAL VALUE TYPE J K E T S, R 52.3 41.2 61.4 40.2 5.76 REFERENCE JUNCTION +15C < TA < +35C TA VA +VS IA 2.5V 7.5V Other thermocouple types may be accommodated with the standard resistance values shown in Table 5. For other ranges of ambient temperature, the equation in Figure 53 may be solved for the optimum values of RT and RA. The microprocessor controlled data acquisition system shown in Figure 54 includes both autozero and autogain capability. By dedicating two of the differential inputs, one to ground and one to the A/D reference, the proper program calibration cycles can eliminate both initial accuracy errors and accuracy errors over temperature. The autozero cycle, in this application, converts a number that appears to be ground and then writes that same number (8-bit) to the AD7524, which eliminates the zero error. Because its output has an inverted scale, the autogain cycle converts the A/D reference and compares it with full scale. A multiplicative correction factor is then computed and applied to subsequent readings. For a comprehensive study of instrumentation amplifier design and applications, refer to the Designer's Guide to Instrumentation Amplifiers (3rd Edition), available free from Analog Devices, Inc. AD580 G = 100 +VS AD590 RA CU 52.3I A + 2.5V 1+ 52.3 R 52.3 + EO - 8.66k AD524 IRON VT CONSTANTAN MEASURING JUNCTION EO = VT - VA + ~V =T - 2.5V RT 1k -VS OUTPUT AMPLIFIER OR METER 00500-053 NOMINAL VALUE 9135 Figure 53. Cold-Junction Compensation The circuit is calibrated by adjusting RT for proper output voltage with the measuring junction at a known reference temperature and the circuit near 25C. If resistors with low temperature coefficients are used, compensation accuracy is to within 0.5C, for temperatures between +15C and +35C. 2 RG2 + 10 16 13 12 11 AD583 VREF AD7507 RG1 A0, A2, EN, A1 AD524 6 9 VIN AGND -VREF AD574A 3 1 - 20k 20k - 1/2 + 5k 10k 1/2 - + AD7524 AD712 LATCH AD712 DECODE CONTROL MICROPROCESSOR 00500-054 ADDRESS BUS Figure 54. Microprocessor Controlled Data Acquisition System Rev. F | Page 23 of 28 AD524 OUTLINE DIMENSIONS 0.005 (0.13) MIN 16 0.080 (2.03) MAX 9 8 PIN 1 0.200 (5.08) MAX 1 0.310 (7.87) 0.220 (5.59) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.840 (21.34) MAX 0.320 (8.13) 0.290 (7.37) 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.100 0.070 (1.78) SEATING (2.54) 0.030 (0.76) PLANE BSC 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 55. 16-Lead Side-Brazed Ceramic Dual In-Line [SBDIP] (D-16) Dimensions shown in inches and (millimeters) 0.100 (2.54) 0.064 (1.63) 0.075 (1.91) REF 0.095 (2.41) 0.075 (1.90) 19 18 3 20 1 4 0.200 (5.08) REF 0.100 (2.54) REF 0.015 (0.38) MIN 0.028 (0.71) 0.022 (0.56) 0.050 (1.27) BSC 0.358 (9.09) 0.342 (8.69) SQ 0.358 (9.09) MAX SQ 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.055 (1.40) 0.045 (1.14) BOTTOM VIEW 14 13 8 9 0.088 (2.24) 0.054 (1.37) 45 TYP 0.150 (3.81) BSC 022106-A CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 56. 20-Terminal Ceramic Leadless Chip Carrier [LCC] (E-20) Dimensions shown in inches and (millimeters) 10.50 (0.4134) 10.10 (0.3976) 16 9 7.60 (0.2992) 7.40 (0.2913) 1 8 10.65 (0.4193) 10.00 (0.3937) 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 2.65 (0.1043) 2.35 (0.0925) 0.75 (0.0295) 0.25 (0.0098) 8 0 0.33 (0.0130) 0.20 (0.0079) 45 SEATING PLANE 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 57. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) Rev. F | Page 24 of 28 032707-B AD524 ORDERING GUIDE Model AD524AD AD524ADZ 1 AD524AE AD524AR-16 AD524AR-16-REEL AD524AR-16-REEL7 AD524ARZ-161 AD524ARZ-16-REEL71 AD524BD AD524BDZ1 AD524BE AD524CD AD524CDZ1 AD524SD AD524SD/883B 5962-8853901EA 2 AD524SE/883B AD524SCHIPS 1 2 Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C -55C to +125C -55C to +125C -55C to +125C Package Description 16-Lead SBDIP 16-Lead SBDIP 20-Terminal LCC 16-Lead SOIC_W 16-Lead SOIC_W, 13" Tape and Reel 16-Lead SOIC_W, 7" Tape and Reel 16-Lead SOIC_W 16-Lead SOIC_W, 7"Tape and Reel 16-Lead SBDIP 16-Lead SBDIP 20-Terminal LCC 16-Lead SBDIP 16-Lead SBDIP 16-Lead SBDIP 16-Lead SBDIP 16-Lead SBDIP 20-Terminal LCC Die Package Option D-16 D-16 E-20 RW-16 RW-16 RW-16 RW-16 RW-16 D-16 D-16 E-20 D-16 D-16 D-16 D-16 D-16 E-20 Z = RoHS Compliant Part. Refer to the official DESC drawing for tested specifications. Rev. F | Page 25 of 28 AD524 NOTES Rev. F | Page 26 of 28 AD524 NOTES Rev. F | Page 27 of 28 AD524 NOTES (c)2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00500-0-11/07(F) Rev. F | Page 28 of 28 |
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